1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to moisture barrier gap fill semiconductor structures and methods for making the same.
2. Description of the Related Art
In the fabrication of semiconductor devices, it is of critical importance that individual devices formed over various layers on a semiconductor substrate are sealed from ambient conditions as well as providing mechanical support for subsequent layers. Conventionally, passivation layers are applied over the topmost surface of integrated circuits to ensure the integrity of the possibly hundreds or thousands of devices and patterned metallization lines that will eventually underlie the passivation layers. Accordingly, the passivation layer must be well suited to completely blanket the top surface of the semiconductor devices. A commonly used passivation layering technique includes depositing an initial phosphorus doped plasma enhanced chemical vapor deposition (PECVD) oxide layer followed by a PECVD silicon nitride layer.
The phosphorus doped oxide layer is used because it is known to absorb moisture and prevent it from migrating and contacting the gate oxides of the underlying active devices as well as the interconnect metallization lines. The silicon nitride layer, on the other hand, is deposited over the phosphorous doped oxide because of its moisture repelling ability. Therefore, a typical passivation layering technique uses the silicon nitride layer as a topmost seal to protect the underlying devices in the first place, and the phosphorous doped oxide as an absorbing shield to prevent any moisture that may have penetrated the silicon nitride layer from migrating to other areas of the semiconductor device.
With this in mind, FIG. 1A is a three-dimensional view of a substrate 10 having a multi-layer passivation 18 blanketed over a pair of metallization lines 12 and 14. For ease of understanding, other well known intermediate dielectric layers that may lie under the pair of metallization lines 12 and 14 will not be described herein. Accordingly, the pair of metallization lines 12 and 14 are patterned over the surface of substrate 10 such that a 90 degree angle is formed when the metallization lines 12 and 14 are patterned in an "L" shape. Because the pair of metallization lines 12 and 14 define a narrow gap separation 15 which may be about 0.5 microns for 0.35 micron technology processes, 0.4 microns for 0.25 micron technology processes, and 0.3 microns for 0.18 micron technology processes, the multi-layer passivation 18 unfortunately tends to produce well known pinch-offs 16 (e.g., also known as voids).
As shown, pinch-off 16 will traverse in parallel along the length of metallization lines 12 and 14 thereby defining a hollow tubular pinch-off region between metallization lines 12 and 14. Fortunately, pinch-off 16 will not provide a moisture paths down into the hollow tubular pinch-off region when the tubular pinch-off regions are defined between lines having minimal geometric bends. However, when the metallization lines 12 and 14 are patterned with more substantial geometrical bends (e.g., the illustrated 90 degree bend), a through gap 16' is unfortunately formed down into the hollow tubular pinch-off region. As a result, through gap 16' provides a channel for moisture and contaminants to penetrate the passivation layer and diffuse through to the underlying insulating layers, metallization and active devices. Further, when a patterning photoresist liquid is coated over the topmost surface of substrate 10, the coated photoresist liquid will typically flow in through gap 16' and become trapped inside of the hollow tubular pinch-off region.
Once the photoresist liquid has served its patterning purpose, the photoresist material is removed in a well known photoresist cleaning operation. However, the cleaning operation will typically be unable to remove the trapped photoresist material lying in the hollow tubular pinch-off region. Consequently, when the pair of metallization lines 12 and 14 and the multi-layer passivation 18 are subsequently annealed to temperatures ranging up to about 400.degree. C., the trapped photoresist material lying within pinch-off 16 will naturally release energy by outgassing the liquid photoresist. In some cases, the outgassing may cause a substantial burst of energy near and around through gap 16'.
FIG. 1B is a top view of the multi-layer passivation 18 that coats the pair of metallization lines 12 and 14 of FIG. 1A. This top view clearly illustrates the possible damage that may occur to multi-layer passivation 18 when the elevated temperatures of the annealing operation are applied to substrate 10. Once the multi-layer passivation 18 becomes damaged to the illustrated magnitude, the multi-layer passivation 18 will no longer serve its intended purpose of protecting the underlying devices and metallization lines 12 and 14 from moisture damage and mobile ions.
To avoid these problems, it has become common practice to deposit thinner multi-layer passivations 18 over an integrated circuit and its associated metallization interconnect lines in an attempt to avoid creating pinch-offs between closely spaced features. Although pinch-offs are no longer created, it has been observed that applying thinner multi-layer passivations 18 has not been sufficient to adequately protect the underlying features during subsequent etching and deposition process steps. At 0.25 micron technology and 0.18 micron technology, this approach may not be extended as the spaces between metal lines approach 0.2 microns. To avoid pinch-offs, extremely thin layers have to be used. These thinner multi-layer passivations 18 are too weak to provide suitable mechanical protection to the chip from subsequent process steps needed for packaging the chips, and are also too thin to provide reliable barriers to moisture and mobile ions. Further, the thinner multi-layer passivations 18 have been in some cases too weak to provide suitable mechanical support for features that may be subsequently patterned over the multi-layer passivation 18.
Another method for preventing pinch-offs between features is to use a high density plasma chemical vapor deposition (HDPCVD) oxide deposition process. As is well known, HDPCVD oxide deposition has been found to be excellent in filling narrow gaps. As a result, the pinch-offs 16 as well as the through gaps 16' of FIG. 1A may be substantially avoided.
FIG. 1C is a cross-sectional view of a semiconductor device having an oxide layer deposited using an HDPCVD process to prevent possible pinch-offs between closely spaced apart features. As shown, a substrate 24 has a metallization line 26 patterned thereon, and an oxide layer 28 deposited over substrate 24 and metallization line 26 using an HDPCVD process. A silicon nitride layer 29 is then deposited over the oxide layer 28 in an attempt to protect the underlying features from moisture and mobile ions. Although the HDPCVD deposited oxide layer 28 provides excellent gap filling performance, oxide layer 28 is not a good barrier against moisture. Therefore, once a patterning and etching step (i.e., etching through silicon nitride layer 29 and oxide layer 28) is performed to define an electrical contact hole to metallization line 26, a moisture and mobile ion path 30 is created through oxide layer 28. The moisture and mobile ion path 30 therefore potentially produces an integrated circuit structure that may be vulnerable to malfunctions and poor performance.
As is well known, a large number of semiconductor devices are typically not packaged in hermetically sealed containers in order to reduce costs, or decrease the size of the packaged device. Therefore, if moisture finds its way into oxide layer 28 through path 30, the gate oxide materials (not shown) of neighboring active devices may absorb the moisture. Unfortunately, when the gate oxides are exposed to moisture, the turn-on threshold voltage of some active devices may shift, while leaving other active devices with non-shifted turn-on threshold voltages. As such, if the turn-on threshold voltages of some active devices are shifted, the integrated circuit devices will have varying turn-on threshold voltages that will unfortunately cause a decline in performance and may cause the circuits deterioration over time. Still further, when the inter-metal oxides absorb moisture, these oxides will unfortunately become brittle and weak which may expose them to performance and functionality deteriorating oxide cracks.
As mentioned above, path 30 may also be a convenient entry way for mobile ions produced by a variety of fabrication and packaging chemicals (e.g., sodium). Typically, mobile ions are introduced during the latter stages of integrated circuit manufacturing where soldering byproducts and handling contaminants are abundant. Once mobile ions find there way into oxide layer 28, these mobile ions may migrate into the gate oxides of neighboring devices, which may also disadvantageously introduced the aforementioned differences in turn-on threshold voltages.
In view of the foregoing, there is a need for semiconductor structures having an excellent barrier against moisture and mobile ions. There is also a need for a method of making semiconductor structures that provide good gap filling performance while maintaining a good barrier against moisture and mobile ions.